The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to fabrication of a field effect transistor with a three sided gate structure in SOI (semiconductor on insulator) technology for minimization of short channel effects for the field effect transistor having scaled down dimensions of tens of nanometers.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scalingdown of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to FIG. 1, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 which is fabricated within a semiconductor substrate 102. The scaled down MOSFET 100 having submicron or nanometer dimensions includes a drain extension 104 and a source extension 106 formed within an active device area 126 of the semiconductor substrate 102. The drain extension 104 and the source extension 106 are shallow junctions to minimize short-channel effects in the MOSFET 100 having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET 100 further includes a drain contact junction 108 with a drain silicide 110 for providing contact to the drain of the MOSFET 100 and includes a source contact junction 112 with a source silicide 114 for providing contact to the source of the MOSFET 100. The drain contact junction 108 and the source contact junction 112 are fabricated as deeper junctions such that a relatively large size of the drain silicide 110 and the source silicide 114 respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET 100.
The MOSFET 100 further includes a gate dielectric 116 and a gate electrode 118 which may be comprised of polysilicon. A gate silicide 120 is formed on the polysilicon gate electrode 118 for providing contact to the gate of the MOSFET 100. The MOSFET 100 is electrically isolated from other integrated circuit devices within the semiconductor substrate 102 by shallow trench isolation structures 121. The shallow trench isolation structures 121 define the active device area 126, within the semiconductor substrate 102, where the MOSFET 100 is fabricated therein.
The MOSFET 100 also includes a spacer 122 disposed on the sidewalls of the gate electrode 118 and the gate dielectric 116. When the spacer 122 is comprised of silicon nitride (SiN), then a spacer liner oxide 124 is deposited as a buffer layer between the spacer 122 and the sidewalls of the gate electrode 118 and the gate dielectric 116.
As the dimensions of the MOSFET 100 are scaled down to tens of nanometers, short channel effects degrade the performance of the MOSFET 100. Short channel effects that result due to the short length of the channel between the drain extension 104 and the source extension 106 of the MOSFET 100 are known to one of ordinary skill in the art of integrated circuit fabrication. Because short channel effects may severely degrade the performance of the MOSFET, mechanisms are desired for minimizing short channel effects in a MOSFET having scaled down dimensions of tens of nanometers.
Accordingly, in a general aspect of the present invention, a semiconductor pillar is formed in SOI (silicon on insulator) technology with a three-sided gate structure. The three-sided gate structure contacts a gate portion of the semiconductor pillar at three sides of the semiconductor pillar for enhanced control of charge accumulation in the gate portion of the semiconductor pillar. With such enhanced control, short channel effects of the MOSFET formed with such a three-sided gate structure are minimized.
In one embodiment of the present invention, for fabricating a field effect transistor, a semiconductor pillar is formed on a layer of insulating material with a top surface and first and second side surfaces of the semiconductor pillar being exposed. A layer of dielectric material is formed on the top surface and the first and second side surfaces of the semiconductor pillar. A layer of conductive material is deposited on the layer of dielectric material on the top surface and the first and second side surfaces of the semiconductor pillar.
A dummy dielectric structure is formed that covers a portion of the layer of conductive material such that a remaining portion of the layer of conductive material on the semiconductor pillar is exposed. The dummy dielectric structure has a predetermined sidewall on the layer of conductive material on the semiconductor pillar.
A layer of hardmask dielectric is deposited on top and on the predetermined sidewall of the dummy dielectric structure and on the remaining portion of the layer of conductive material that is exposed. The layer of hardmask dielectric is anisotropically etched such that the hardmask dielectric remains at the predetermined sidewall of the dummy dielectric structure to form a spacer of hardmask dielectric.
The dummy dielectric structure is etched away such that the spacer of hardmask dielectric remains. The spacer of hardmask dielectric covers the layer of conductive material on the top surface and the first and second side surfaces of the semiconductor pillar at a gate portion of the semiconductor pillar. Any exposed region of the layer of conductive material and the layer of dielectric material not covered by the spacer of hardmask dielectric is etched away such that the conductive material and the dielectric material remain on the top surface and the first and second side surfaces at the gate portion of the semiconductor pillar The conductive material that remains on the top surface and the first and second side surfaces at the gate portion of the semiconductor pillar forms a three-sided gate structure of the field effect transistor. In addition, the dielectric material that remains on the top surface and the first and second side surfaces at the gate portion of the semiconductor pillar forms a three-sided gate dielectric of the field effect transistor.
The present invention may be used to particular advantage when the semiconductor pillar is comprised of silicon, the layer of insulating material is comprised of silicon dioxide (SiO2), the layer of dielectric material is comprised of silicon dioxide (SiO2), the layer of conductive material is comprised of polysilicon, the dummy dielectric structure is comprised of silicon nitride (Si3N4), and/or the layer of hardmask dielectric is comprised of silicon dioxide (SiO2).
In another embodiment of the present invention, for fabricating a MOSFET (metal oxide semiconductor field effect transistor), the spacer of the hardmask dielectric is etched away. A drain contact pad is formed at a first end of the semiconductor pillar, and a source contact pad is formed at a second end of the semiconductor pillar. A dopant is implanted into exposed regions of the semiconductor pillar to form a drain region within the semiconductor pillar at a first side of the gate portion toward the first end of the semiconductor pillar, and to form a source region within the semiconductor pillar at a second side of the gate portion toward the second end of the semiconductor pillar. A gate spacer is formed to surround the gate structure and the gate dielectric. A gate silicide is formed with the gate structure, a drain silicide is formed with the drain region, and a source silicide is formed with the source region.
In this manner, the three-sided gate structure contacts a gate portion of the semiconductor pillar at three sides of the semiconductor pillar for enhanced control of charge accumulation in the gate portion of the semiconductor pillar. With such enhanced control, short channel effects of the MOSFET formed with such a three-sided gate structure are minimized.